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NTD78N03 Power MOSFET
25 V, 78 A, Single N-Channel, DPAK
Features
* Low RDS(on) * Optimized Gate Charge * Pb-Free Packages are Available
Applications
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V(BR)DSS 25 V RDS(on) TYP 4.6 @ 10 V 6.5 @ 4.5 V D ID MAX 78 A
* Desktop VCORE * DC-DC Converters * Low Side Switch
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Note 1) Power Dissipation (Note 1) Continuous Drain Current (Note 2) Power Dissipation (Note 2) Continuous Drain Current (RqJC) Power Dissipation (RqJC) Pulsed Drain Current Current Limited by Package Drain to Source dV/dt Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain-to-Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 5.0 mH, IL(pk) = 17 A, RG = 25 W) Lead Temperature for Soldering Purposes (1/8 from case for 10 s) TA = 25C TA = 85C TA = 25C TA = 25C Steady y State St t TA = 85C TA = 25C TC = 25C TC = 85C TC = 25C tp = 10 ms TA = 25C PD IDM IDmaxPkg dV/dt TJ, Tstg IS EAS PD ID PD ID Symbol VDSS VGS ID Value 25 "20 14.8 11.5 2.3 11.4 8.8 1.4 78 56 64 88 32 2.0 -55 to 175 78 722.5 W A A V/ns C A mJ W A W Unit V V A
N-Channel G S 4 4 4
A 12 3 CASE 369C DPAK (Bend Lead) STYLE 2 1 1 2 23
3 CASE 369D DPAK (Straight Lead) STYLE 2
CASE 369AC 3 IPAK (Straight Lead)
MARKING DIAGRAMS & PIN ASSIGNMENTS
4 Drain YWW 78 N03 3 Source 1 Gate 3 Source 2 Drain Y = Year WW = Work Week 78N03 = Device Code Publication Order Number: NTD78N03/D 4 Drain
TL
260
C
1 Gate
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface-mounted on FR4 board using the minimum recommended pad size (Cu area = TBD in sq).
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2005
1
February, 2005 - Rev. 0
YWW 78 N03 2 Drain
ORDERING INFORMATION
NTD78N03
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Junction-to-Case (Drain) Junction-to-Ambient - Steady State (Note 3) Junction-to-Ambient - Steady State (Note 4) Symbol RqJC RqJA RqJA Value 1.95 65 110 Unit C/W C/
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS VGS = 0 V, VDS = 20 V TJ = 25C TJ = 125C VGS = 0 V, ID = 250 mA 25 24 1.5 10 "100 nA V mV/C mA Symbol Test Condition Min Typ Max Unit
Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance
IGSS
VDS = 0 V, VGS = "20 V
VGS(TH) VGS(TH)/TJ RDS(on) ()
VGS = VDS, ID = 250 mA
1.0
1.6 -5.0
3.0
V mV/C
VGS = 10 V, ID = 78 A VGS = 4.5 V, ID = 36 A
4.6 6.5 22
6.0 7.8
mW
Forward Transconductance
gFS
VDS = 10 V, ID = 15 A
S
CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = 20 A TJ = 25C TJ = 125C 0.83 0.7 39 VGS = 0 V, dIs/dt = 100 A/ms, IS = 20 A 17.8 21 33 nC ns 1.0 V td(on) tr td(off) tf VGS = 4.5 V, VDS = 20 V, ID = 20 A, RG = 3.0 W 11 68 23 42 ns Ciss Coss Crss QG(TOT) QG(TH) QGS QGD VGS = 4.5 V, VDS = 20 V, ID = 20 A VGS = 0 V, f = 1.0 MHz, V 1 0 MH VDS = 12 V 1920 960 420 25.5 2.4 5.3 18.2 35 nC pF
Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time 3. 4. 5. 6.
tRR ta tb QRR
Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). Surface-mounted on FR4 board using the minimum recommended pad size (Cu area = TBD in sq). Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. Switching characteristics are independent of operating junction temperatures.
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2
NTD78N03
100 90 ID, DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 0 2 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 3V TJ = 25C 2.6 V 10 9V 3.4 V 3.2 V VGS = 4 V 4.5 V 5V 3.8 V 3.6 V ID, DRAIN CURRENT (AMPS) 160 150 VDS 10 V 140 130 120 110 100 90 80 70 60 50 TJ = 125C 40 30 TJ = 25C 20 TJ = -55C 10 0 0 3 1 2 4
5
6
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
0.01 VGS = 10 V TJ = 125C
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
0.015 TJ = 25C
0.009
0.008 0.007
0.01
0.006
VGS = 4.5 V
TJ = 25C
0.005 0.004 0.003 TJ = -55C
VGS = 10 V 0.005
0.002 0.001 0 10 20 30 40 50 60 70 80
0 55
60
65
70
75
80
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 3. On-Resistance versus Drain Current and Temperature
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 3 2.5 2 1.5 1 0.5 0 -50 10 ID = 78 A VDS = 4.5 V IDSS, LEAKAGE (nA) 10000
Figure 4. On-Resistance versus Drain Current and Gate Voltage
100000 VGS = 0 V
TJ = 150C 1000 TJ = 125C
100
-25
0
25
50
75
100
125
150
175
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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NTD78N03
VGS, GATE-TO-SOURCE VOLTAGE (V) 6000 5000 C, CAPACITANCE (pF) Ciss 4000 Crss 3000 2000 1000 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss Coss VDS = 0 V VGS = 0 V 8 VDS 6 TJ = 25C QT 20 VDS, DRAIN-TO-SOURCE VOLTAGE (V)
15
4
VGS Q1 Q2
10
2 ID = 20 A TJ = 25C 0 0 5 10 15 20 25 30
5
0 35
Qg, TOTAL GATE CHARGE (nC)
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge
1000 IS, SOURCE CURRENT (AMPS) VDS = 20 V ID = 20 A VGS = 4.5 V t, TIME (ns) 100 tr tf td(off) 10 td(on)
80 VGS = 0 V 70 T = 25C J 60 50 40 30 20 10 0 0.5 0.6 0.7 0.8 0.9 1.1 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (V) 1.2
1 1 10 RG, GATE RESISTANCE (OHMS) 100
Figure 9. Resistive Switching Time Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
EAS, SINGLE PULSE DRAIN-TO- SOURCE AVALANCHE ENERGY (mJ)
1000 I D, DRAIN CURRENT (AMPS) 10 ms 100 100 ms 1 ms 10 VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 10 ms dc
800 700 600 500 400 300 200 100 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) 175 ID = 78 A
1
0.1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
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NTD78N03
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 13. Diode Reverse Recovery Waveform
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE DUTY CYCLE 100 D = 0.5 0.2 0.1 0.05 0.02 0.01
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT
10
1
P(pk) t2 DUTY CYCLE, D = t1/t2 1E-03 1E-02 1E-01 t, TIME (seconds) 1E+00 t1
0.1 SINGLE PULSE 0.01 1E-05 1E-04
RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+02 1E+03
1E+01
Figure 14. Thermal Response - Various Duty Cycles
ORDERING INFORMATION
Order Number NTD78N03 NTD78N03T4 NTD78N03T4G NTD78N03-1 NTD78N03-1G NTD78N03-35 NTD78N03-35G Package DPAK DPAK DPAK (Pb-Free) DPAK Straight Lead DPAK Straight Lead (Pb-Free) DPAK-3 Straight Lead (3.5 " 0.15 mm) DPAK-3 Straight Lead (3.5 " 0.15 mm) (Pb-Free) Shipping 75 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 75 Units/Rail 75 Units/Rail 75 Units/Rail 75 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NTD78N03
PACKAGE DIMENSIONS
DPAK CASE 369C-01 ISSUE O
-T- B V R
4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
C E
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005) T
DIM A B C D E F G H J K L R S U V Z
M
SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NTD78N03
PACKAGE DIMENSIONS
DPAK CASE 369D-01 ISSUE B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
B V R
4
C E
Z A
3
S -T-
SEATING PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 ---
MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
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NTD78N03
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD CASE 369AC-01 ISSUE O
NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25
B V R
C E
A
SEATING PLANE
W F G
K J H D
3 PL
0.13 (0.005) W
DIM A B C D E F G H J K R V W
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NTD78N03/D

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